CINSEL=CAPN_0_FOR_TIMERN, CTMODE=TIMER_MODE_EVERY_RI
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
| CTMODE | Counter/Timer Mode This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 (TIMER_MODE_EVERY_RI): Timer Mode: every rising PCLK edge 1 (RISING): Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 2 (FALLING): Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 3 (DUALEDGE): Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. |
| CINSEL | Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 0 (CAPN_0_FOR_TIMERN): CAPn.0 for TIMERn 1 (CAPN_1_FOR_TIMERN): CAPn.1 for TIMERn 2 (RESERVED): Reserved 3 (RESERVED): Reserved |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |